1. Field of the Invention
The present invention relates to a patterning method and a method of manufacturing a TFT (thin film transistor) matrix substrate and, more particularly, to a patterning method for connecting patterns to form a single pattern as a whole and a method of manufacturing a thin film transistor substrate utilizing the patterning method.
2. Description of the Related Art
TFT matrix type color liquid crystal displays have been spreading recently as displays of personal computers and wall-mount televisions. This has resulted in a trend toward liquid crystal displays with greater screens.
In order to manufacture such displays at low cost, it is important to form TFT matrices with less processing steps and higher yield, which is primarily achieved by photolithographic techniques utilizing reticles (exposure mask) capable of transferring a multiplicity of patterns simultaneously. Normally, one reticle (called one layer) is used for one patterning step.
In the case of a large screen which has a great substrate, it is difficult to transfer the entire pattern of one layer at a time for reasons associated with the structure of the exposure device. For this reason, the entire patterned region of one layer is divided into a plurality of sub-regions, and a plurality of reticles are provided to process each of the sub-regions. When the entire pattern is formed, each of the sub-regions of the same resist film is separately exposed by masking regions other than the sub-region to be exposed to form the entire pattern.
FIG. 4 schematically shows a TFT matrix substrate 50. The number of pixels in FIG. 4 is shown in a simplified manner. Basic pixel units 40 driven by TFTs 36 are arranged in the form of a matrix of 6 rowsxc3x979 columns. The configuration will now be briefly described. Gate bus lines 32 and drain bus lines 34 are arranged on a glass substrate 30 perpendicularly to each other, and TFTs 36 (the configuration of which will be described later) are provided near intersections between the gate bus lines 32 and drain bus lines 34. The gates of the TFTs 36 are connected to the gate bus lines 32, and the drains are connected to the drain bus lines 34. Further, source electrodes of the TFTs 36 are connected to pixel electrodes 38. A unit region formed by a TFT 36, pixel electrode 38, gate bus line 32 and drain bus line 34 connected each other is referred to as xe2x80x9cbasicxe2x80x9d pixel unit"", and a pattern in such a region is referred to as xe2x80x9cbasic unit patternxe2x80x9d.
When the TFT matrix as shown in FIG. 4 is formed using two reticles, a method may be used in which the matrix is simply divided into two regions, i.e., the region of the first through fourth columns (left region) and the region of the fifth through ninth columns (right region) along a linear border line. As will be apparent from the plan view in FIG. 5 and the sectional view in FIG. 6 (sectional view taken along the line Axe2x80x94A in FIG. 5), a TFT 36 is formed such that a gate electrode 32 (a gate bus line 32) overlaps a source electrode 36S and a drain electrode 36D in consideration to alignment accuracy and, as a result, a floating capacity Cgs is generated between the gate electrode 32 and source electrode 36S. When the left and right regions described above are separately aligned to solve this, a difference may occur in the width of an overlap of the source electrode 36S and gate electrode 32 between the TFTs 36 in the left region and the TFTs 36 in the right region. In this case, since the TFTs 36 in the left and right regions have different floating capacities Cgs, those regions will have different source electrode, which causes a difference in transmittance between them. As a result, a difference in luminance occurs between the two regions to cause unevenness of display. While the above example is divided in the lateral direction, division in the longitudinal direction may be adopted in addition to lateral division in practice because of a greater number of pixels, in which case misalignment can occur in all directions.
As a method of solving such unevenness of display, patterning methods are disclosed in Japanese Patent Laid-Open No. 236930/1997 and so on in which unit patterns of different exposure masks are mixed at a joint between groups of unit patterns formed by different exposure masks.
FIG. 7 is a schematic illustration of the conventional technique disclosed in the above-cited publication in which two (a pair of) reticles are shown. Reticles RTa3 and RTb3 are provided to form a TFT matrix of 6 rowsxc3x976 columns. Although there is exposure steps for a plurality of layers and different exposure patterns exist for respective layers in practice, for simplicity of description, simplified patterns of gate bus lines 66, drain bus lines, TFTs 70 and pixel electrodes are shown here to clearly indicate basic pixel units 72.
The TFT matrix having 6 columns is divided in two columns to define a first region (the first and second columns), a second region (the fifth and sixth columns) and a third region (the third and fourth columns), and the third region is a boundary portion to serve as a joint during pattern formation using the two reticles. Therefore, in the reticle RTa3, patterning regions 78 for exposing the basic pixel units 72 are provided in a region 100 corresponding to the first region, and patterning regions 78 and shading regions 76 which are non-patterning regions where no exposure occurs are provided in a staggered configuration in a region 300axe2x80x2 corresponding to the third region. In the reticle RTb3, patterning regions 78 for exposing the basic pixel units 72 are provided in a region 200 corresponding to the second region, and patterning regions 78 and shading regions 76 which are non-patterning regions where no exposure occurs are provided in a staggered configuration that is the reverse of (complement to) that in the reticle RTa3 in the region 300axe2x80x2 corresponding to the third region. Therefore, the basic pixel units 72 in the third region are exposed and patterned when one of the reticles RTa3 and RTb3 is used and are not exposed when the other reticle is used because of the shading regions.
When such a boundary portion is provided to mix unit patterns associated with different exposure masks in the boundary portion, it is difficult to recognize a clear boundary even if any difference in luminance exits between the patterns formed using the different masks.
FIGS. 8 and 9 show parts of reticles used in a specific application of the patterning method shown in FIG. 7. Reticles RTa4 and RTb4 are provided to form a TFT matrix pattern having nine columns as shown in FIG. 4 in which the first and second columns are a first region; the eighth and ninth columns are a second region; and the third through seventh columns are a third region.
The reticle RTa4 shown in FIG. 8 is provided to pattern the first and third regions, and patterning regions 78 associated with basic pixel units 72 are provided in a portion corresponding to the first region (the first and second columns). In a portion corresponding to the third region (the third through seventh columns), there is provided patterning regions 78 associated with the regions of basic pixel units 72 and shading regions 76 similarly associated with the regions of basic pixel units 72 in a staggered configuration.
The reticle RTb4 shown in FIG. 9 is provided to pattern the second and third regions, and patterning regions 78 associated with basic pixel units 72 are provided in a portion corresponding to the third region (the eighth and ninth columns). In a portion corresponding to the second region (the third through seventh columns), there is provided patterning regions 78 associated with the regions of basic pixel units 72 and shading regions 76 similarly associated with the regions of basic pixel units 72 in a staggered configuration which is complementary to that of the reticle RTa4.
Specifically, the reticles RTa4 and RTb4 are used for patterning drain electrodes, source electrodes, drain bus lines and storage capacitor electrodes for a storage capacitor at steps for manufacturing a TFT matrix. That is, storage capacitor electrodes 42, source electrodes 36S, drain electrodes 36D and drain bus lines 34 in FIGS. 8 and 9 are patterned at the same step, although the process will be detailed later. In a basic pixel unit 72 (patterning region 78), a shading pattern associated with a storage capacitor electrode 42, source electrode 36S, drain electrode 36D and drain bus line 34 is formed.
FIG. 10A is an enlarged view of the circled portion in FIG. 8, and FIG. 10B is a sectional view taken along the line Xxe2x80x94X in FIG. 10A.
Referring to FIG. 1A, in a portion where a shading region 76 is provided on the left side and adjacent to a patterning region 78, a shading pattern for the patterning region 78 associated with a desired drain bus line pattern extends along and close to an edge of the shading pattern of the shading region 76 on the right side of the same. Further, a desired shading pattern associated with a storage capacitor electrode pattern having a desired storage capacitor is formed on the right side of the same. Referring to FIG. 10B, the reticle RTa4 is a transparent substrate 80 made of glass or the like formed with a shading pattern 82 constituted by a metal film having a light-blocking property such as chromium.
Next, referring to FIG. 11A and FIG. 11B, in a portion where a shading region 76 is provided on the right side and adjacent to a patterning region 78, a desired shading pattern corresponding to a storage capacitor electrode pattern of the patterning region 78 on the left side of the shading pattern of the shading region 76. Further, similar to the reticle Rta4, in a reticle RTb4, a shading pattern 82 is constituted by a metal film having a light-blocking property such as chromium on a transparent substrate 80 made of glass or the like.
FIG. 12 illustrates the shading pattern of the reticle RTb4 shown in FIG. 11A overlapped with the shading pattern of the patterning region of the reticle RTa4 in FIG. 10A. An interval L between an edge of the shading pattern of the reticle RTa4 associated with a data bus line and an edge of the shading pattern of the shading region of the reticle RTb4 depends on the desired pattern or a pattern interval G between the storage capacitor electrode and data bus line. Therefore, the interval L becomes small as the interval G becomes small as a result of an increase in the fineness of the patterns. The interval L can become small also due to a misalignment of the reticles.
When the interval L becomes small, light can enter to expose a region which should not be exposed as a result of diffraction from the edge of the shading pattern of the shading region 76 during exposure of one of the reticles (the reticle RTb4, for example). Therefore, for example, in the case of a data bus line, a narrow pattern smaller than a desired pattern width can be formed.
The present invention was made taking the above-described problems in the related art into consideration, and it is an object of the invention to provide a patterning method which makes it possible to form a desired preferable pattern without any reduction of the pattern at a boundary where a group of patterns formed using a plurality of exposure masks are joined and to provide a method of forming a TFT matrix substrate.
In a first aspect of the invention, the above-described problems are solved by a patterning method that is characterized as follows.
There is provided a patterning method for forming a group of patterns in which first patterns serving as basic units are repetitively arranged using a plurality of exposure masks, in which a third region sandwiched between a first region exposed with a first mask and a second region exposed with a second mask is exposed in a complementary manner with the first and second exposure masks, repetitive unit patterns for exposing the third region being different from the first patterns.
In the first aspect of the invention, patterning regions and shading regions are provided in the third region when it is exposed. A desired pattern of a patterning region is not affected by the shading region when exposure is performed the other mask, which makes it possible to achieve the desired pattern because no reduction of the pattern occurs due to unnecessary exposure.
In a second aspect of the invention, the above-described problems are solved by a method of manufacturing a thin film transistor matrix substrate that is characterized as follows.
There is provided a method of manufacturing a thin film transistor matrix substrate having the step of forming at least either gate bus lines or drain bus lines using the patterning method in the first aspect of the invention.
In the second aspect of the invention, a gate bus line, drain bus line or the like is provided at an edge of a basic pixel unit within the region of the same. Therefore, if the patterning regions repetitively provided in the third region are provided with in the pattern of the basic pixel unit, the patterns of the gate bus line and drain bus line can be adversely affected when exposed with a plurality of exposure masks. However, the use of a pattern that is different from the basic pixel unit makes it possible to achieve a desired pattern without any influence.